`include "aLU_32bit.v"
module alu_tb;

  reg signed [31:0] a;
  reg signed [31:0] b;
  reg [2:0] op;
  wire signed [31:0] out;
  wire zero;
  wire overflow;

  alu alu_tb (
    .a(a),
    .b(b),
    .op(op),
    .out(out),
    .zero(zero),
    .overflow(overflow)
  );

  integer i;

  initial begin
    $display("Testing aLU...");

    // Test addition
    $display("Testing addition...");
    for (i = 0; i < 10; i = i + 1) begin
      a = $random;
      b = $random;
      op = 0; // addition
      #1;
      $display("  %d + %d = %d", a, b, out);
      $display("  zero = %b, overflow = %b", zero, overflow);
      #10;
    end

    // Test subtraction
    $display("Testing subtraction...");
    for (i = 0; i < 10; i = i + 1) begin
      a = $random;
      b = $random;
      op = 1; // Subtraction
      #1;
      $display("  %d - %d = %d", a, b, out);
      $display("  zero = %b, overflow = %b", zero, overflow);
      #10;
    end

    // Test bitwise aND
    $display("Testing bitwise aND...");
    for (i = 0; i < 10; i = i + 1) begin
      a = $random;
      b = $random;
      op = 2; // bitwise aND
      #1;
      $display("  %b & %b = %b", a, b, out);
      $display("  zero = %b, overflow = %b", zero, overflow);
      #10;
    end

    // Test bitwise OR
    $display("Testing bitwise OR...");
    for (i = 0; i < 10; i = i + 1) begin
      a = $random;
      b = $random;
      op = 3; // bitwise OR
      #1;
      $display("  %b | %b = %b", a, b, out);
      $display("  zero = %b, overflow = %b", zero, overflow);
      #10;
    end

    $finish;
  end

endmodule
